Systems that include integrated circuit (IC) devices typically include decoupling capacitors (also known as bypass capacitors) as well. A decoupling capacitor is a capacitor coupled between the power and ground pins (i.e., terminals) of a packaged IC to reduce noise on the power system within the IC. (The word “coupled” as used herein means “electrically connected in such as way as to pass direct current” as opposed to “capacitively coupled”, except where the phrase “capacitively coupled” is explicitly used.) While in some cases the IC itself includes some decoupling capacitance, the amount of capacitance required is such that one or more additional decoupling capacitors are usually added external to the packaged device.
In the past, the location of these decoupling capacitors was a less important issue. The switching frequency of a device was relatively low, e.g., in the range of hundreds of kHz (kilohertz) to tens of MHz (megahertz). The transient currents within the device were also relatively low. Hence, parasitic inductance in the printed circuit board (PCB) mountings was not an important consideration. For example, for an IC mounted in a medium-performance package, whether leaded or surface-mounted to the PCB, a 0.1 uF (microfarad) decoupling capacitor could typically be mounted on the PCB anywhere within a few inches of the packaged IC.
Many ICs now operate at clock frequencies in the hundreds of MHz. At these higher frequencies, transient currents are significantly higher than in the past, and parasitic inductance is a much more important issue. Parasitic inductance within the capacitors themselves has been reduced by improving the packaging of the capacitors, e.g., by using only surface-mount packages and by reducing the size of the packages. (Smaller packages inherently have a lower parasitic inductance.) Parasitic inductance within the PCB mountings has also been reduced through improved layout techniques, e.g., by using dedicated power planes in the PCB, by improving capacitor land geometries, and by careful placement of the capacitors to reduce the distance between the packaged IC and the capacitors.
However, as operating frequencies continue to increase, even these measures become inadequate. One bottleneck in the current path between a decoupling capacitor and the associated packaged IC are the vias that transport charge from the capacitor lands through the PCB to the power planes, and then from the power planes through the PCB to the device. These vias can contribute parasitic inductance in the range of 1.5 nH (nanohenrys) each. If this via inductance could be reduced or eliminated, providing for high-frequency transient current would be much easier.
Therefore, it is desirable to provide systems and structures that provide decoupling capacitance to IC devices with reduced capacitor parasitic inductance. It is further desirable to reduce via parasitic inductance in these systems and structures.